Club 100 Library, Modem 415-939-1246 DISAVE.BA is Chris Morgans disassembler revised and made to open a file called "SAVE.DO" for printing its output. The "[ ]" following a mnemonic is a window in which the byte for that instruction is displayed in Hex. The "{1} or {0}" following a mnemonic is the appropriate flag for that instruction. The output and input addresses are in decimal were Morgans were in Hex, I find this easier to work with since we "PEEK" and "CALL" our machines in decimal. Notice that if you ignore the left most digit in lines 1000 - 1255 they will correspond to the mnemonics decimal value. The following is a list of definitions for mnemonics thanks to Drew Blanchar, manager of our workshops. I have condensed it a little and made a few changes, one of which is the word "RAM" instead of "mem". I also used "RAM" instead of "M" in DISAVE.BA, a little unorthodox but it bring things together. If a register pair is used to calculate an address I wrote "D&E" were as if a register pair is simply used to store or load 2 bytes I wrote "D/E". 8085 MACHINE LANGUAGE Dec Hex Operation 0 00 NOP no operation 1 01 LXI load next 2 bytes into B/C 2 02 STAX store A in RAM at address found in B&C 3 03 INX increment B/C 4 04 INR increment B 5 05 DCR decrement B 6 06 MVI load B with next byte 7 07 RLC rotate A left with branch carry 8 08 9 09 DAD add B/C to RAM at address found in H&L 10 0A LDAX load A from RAM at address found in B&C 11 0B DCX decrement B/C 12 0C INR increment C 13 0D DCR decrement C 14 0E MVI load C with next byte 15 0F RRC rotate A right with branch carry 16 10 17 11 LXI load next 2 bytes into D/E 18 12 STAX store A in RAM at address found in D&E 19 13 INX increment D/E 20 14 INR increment D 21 15 DCR decrement D 22 16 MVI load D with next byte 23 17 RAL rotate A left (w/carry) 24 18 25 19 DAD add D/E to RAM at address found in H&L 26 1A LDAX load A from RAM at address found in D&E 27 1B DCX decrement D/E 28 1C INR increment E 29 1D DCR decrement E 30 1E MVI load E with next byte 31 1F RAR rotate A right (w/carry) 32 20 RIM read interrupt mask 33 21 LXI load next 2 bytes into H/L 34 22 SHLD store H/L in RAM at address in next 2 bytes 35 23 INX increment H/L 36 24 INR increment H 37 25 DCR decrement H 38 26 MVI load H with next byte 39 27 DAA decimal adjust A 40 28 41 29 DAD add H/L to RAM at address found in H&L 42 2A LHLD load H/L from RAM at address in next 2 bytes 43 2B DCX decrement H/L 44 2C INR increment L 45 2D DCR decrement L 46 2E MVI load L with next byte 47 2F CMA 1's compliment of register A 48 30 SIM set interrupt mask 49 31 LXI load next 2 bytes into SP 50 32 STA store A in RAM at address in next 2 bytes 51 33 INX increment SP 52 34 INR increment RAM at address found in H&L 53 35 DCR decrement RAM at address found in H&L 54 36 MVI store next byte in RAM at address found in H&L 55 37 STC set Carry flag to 1 56 38 57 39 DAD add SP to RAM at address found in H&L 58 3A LDA load A from RAM at address in next 2 bytes 59 3B DCX decrement SP 60 3C INR increment A 61 3D DCR decrement A 62 3E MVI load A with next byte 63 3F CMC 1's compliment of Carry flag 64 40 MOV load B from B 65 41 MOV load B from C 66 42 MOV load B from D 67 43 MOV load B from E 68 44 MOV load B from H 69 45 MOV load B from L 70 46 MOV load B from RAM at address found in H&L 71 47 MOV load B from A 72 48 MOV load C from B 73 49 MOV load C from C 74 4A MOV load C from D 75 4B MOV load C from E 76 4C MOV load C from H 77 4D MOV load C from L 78 4E MOV load C from RAM at address found in H&L 79 4F MOV load C from A 80 50 MOV load D from B 81 51 MOV load D from C 82 52 MOV load D from D 83 53 MOV load D from E 84 54 MOV load D from H 85 55 MOV load D from L 86 56 MOV load D from RAM at address found in H&L 87 57 MOV load D from A 88 58 MOV load E from B 89 59 MOV load E from C 90 5A MOV load E from D 91 5B MOV load E from E 92 5C MOV load E from H 93 5D MOV load E from L 94 5E MOV load E from RAM at address found in H&L 95 5F MOV load E from A 96 60 MOV load H from B 97 61 MOV load H from C 98 62 MOV load H from D 99 63 MOV load H from E 100 64 MOV load H from H 101 65 MOV load H from L 102 66 MOV load H from RAM at address found in H&L 103 67 MOV load H from A 104 68 MOV load L from B 105 69 MOV load L from C 106 6A MOV load L from D 107 6B MOV load L from E 108 6C MOV load L from H 109 6D MOV load L from L 110 6E MOV load L from RAM at address found in H&L 111 6F MOV load L from A 112 70 MOV store B in RAM at address found in H&L 113 71 MOV store C in RAM at address found in H&L 114 72 MOV store D in RAM at address found in H&L 115 73 MOV store E in RAM at address found in H&L 116 74 MOV store H in RAM at address found in H&L 117 75 MOV store L in RAM at address found in H&L 118 76 HLT halt 119 77 MOV store A in RAM at address found in H&L 120 78 MOV load A from B 121 79 MOV load A from C 122 7A MOV load A from D 123 7B MOV load A from E 124 7C MOV load A from H 125 7D MOV load A from L 126 7E MOV load A from RAM at address found in H&L 127 7F MOV load A from A 128 80 ADD add B to A 129 81 ADD add C to A 130 82 ADD add D to A 131 83 ADD add E to A 132 84 ADD add H to A 133 85 ADD add L to A 134 86 ADD add byte at address found in H&L to A 135 87 ADD add A to A 136 88 ADC add (w/carry) B to A 137 89 ADC add (w/carry) C to A 138 8A ADC add (w/carry) D to A 139 8B ADC add (w/carry) E to A 140 8C ADC add (w/carry) H to A 141 8D ADC add (w/carry) L to A 142 8E ADC add (w/carry) byte at address found in H&L to A 143 8F ADC add (w/carry) A to A 144 90 SUB subtract B from A 145 91 SUB subtract C from A 146 92 SUB subtract D from A 147 93 SUB subtract E from A 148 94 SUB subtract H from A 149 95 SUB subtract L from A 150 96 SUB subtract byte at address found in H&L from A 151 97 SUB subtract A from A 152 98 SBB subtract B from A (w/borrow) 153 99 SBB subtract C from A (w/borrow) 154 9A SBB subtract D from A (w/borrow) 155 9B SBB subtract E from A (w/borrow) 156 9C SBB subtract H from A (w/borrow) 157 9D SBB subtract L from A (w/borrow) 158 9E SBB subtract byte at address found in H&L from A (w/borrow) 159 9F SBB subtract A from A (w/borrow) 160 A0 ANA "AND" B with A 161 A1 ANA "AND" C with A 162 A2 ANA "AND" D with A 163 A3 ANA "AND" E with A 164 A4 ANA "AND" H with A 165 A5 ANA "AND" L with A 166 A6 ANA "AND" byte at address found in H&L with A 167 A7 ANA "AND" A with A 168 A8 XRA "exclusive-OR" B with A 169 A9 XRA "exclusive-OR" C with A 170 AA XRA "exclusive-OR" D with A 171 AB XRA "exclusive-OR" E with A 172 AC XRA "exclusive-OR" H with A 173 AD XRA "exclusive-OR" L with A 174 AE XRA "exclusive-OR" byte at address found in H&L with A 175 AF XRA "exclusive-OR" A with A 176 B0 ORA "OR" B with A 177 B1 ORA "OR" C with A 178 B2 ORA "OR" D with A 179 B3 ORA "OR" E with A 180 B4 ORA "OR" H with A 181 B5 ORA "OR" L with A 182 B6 ORA "OR" byte at address found in H&L with A 183 B7 ORA "OR" A with A 184 B8 CMP compare B with A 185 B9 CMP compare C with A 186 BA CMP compare D with A 187 BB CMP compare E with A 188 BC CMP compare H with A 189 BD CMP compare L with A 190 BE CMP compare byte at address found in H&L with A 191 BF CMP compare A with A 192 C0 RNZ return from subroutine if Zero flag=0 193 C1 POP load B/C from STACK, increment SP by 2 194 C2 JNZ jump to address in next 2 bytes if Zero flag=0 195 C3 JMP jump to address in next 2 bytes 196 C4 CNZ call subroutine at address in next 2 bytes if Zero flag=0 197 C5 PUSH load B/C onto STACK, decrement SP by 2 198 C6 ADI add next byte to register A 199 C7 RST restart 0 200 C8 RZ return from subroutine if Zero flag=1 201 C9 RET return from subroutine 202 CA JZ jump to address in next 2 bytes if Zero flag=1 203 CB 204 CC CZ jump to subroutine at address in next 2 bytes if Zero flag=1 205 CD CALL subroutine at address in next 2 bytes 206 CE ACI add next byte (w/carry) to register A 207 CF RST restart 1 208 D0 RNC return from subroutine if Carry flag=0 209 D1 POP load D/E from STACK, increment SP by 2 210 D2 JNC jump to address in next 2 bytes if Carry flag=0 211 D3 OUT load register A to the I/O port of the address in next byte 212 D4 CNC call subroutine at address in next 2 bytes if Carry flag=0 213 D5 PUSH load D/E onto STACK, decrement SP by 2 214 D6 SUI subtract next byte from regiter A 215 D7 RST restart 2 216 D8 RC return from subroutine if Carry flag=1 217 D9 218 DA JC jump to address in next 2 bytes if Carry flag=1 219 DB IN load register A from the I/O port of the address in next byte 220 DC CC call subroutine at address in next 2 bytes if Carry flag=1 221 DD 222 DE SBI subtract next byte from register A (w/borrow) 223 DF RST restart 3 224 E0 RPO return from subroutine if odd parity 225 E1 POP load H/L from STACK, increment SP by 2 226 E2 JPO jump to address in next 2 bytes if odd parity 227 E3 XTHL exchange H/L with STACK 228 E4 CPO call subroutine at address in next 2 bytes if odd parity 229 E5 PUSH load H/L onto STACK, decrement SP by 2 230 E6 ANI "AND" next byte with register A 231 E7 RST restart 4 232 E8 RPE return from subroutine if even parity 233 E9 PCHL load PC from H/L 234 EA JPE jump to address in next 2 bytes if even parity 235 EB XCHG exchange D/E with H/L 236 EC CPE call subroutine at address in next 2 bytes if even parity 237 ED 238 EE XRI "exclusive-OR" next byte with register A 239 EF RST restart 5 240 F0 RP return from subroutine if Sign flag=0 241 F1 POP load PSW from STACK, increment SP by 2 242 F2 JP jump to address in next 2 bytes if Sign flag=0 243 F3 DI disable interrupts 244 F4 CP call subroutine at address in next 2 bytes if Sign flag=0 245 F5 PUSH load PSW onto STACK, decrement SP by 2 246 F6 ORI "OR" next byte with register A 247 F7 RST restart 6 248 F8 RM return from subroutine if Sign flag=1 249 F9 SPHL load SP from H/L 250 FA JM jump to address in next 2 bytes if Sign flag=1 251 FB EI enable interrupts 252 FC CM call subroutine at address in next 2 bytes if Sign flag=1 253 FD 254 FE CPI compare next byte with register A 255 FF RST restart 7 8085 REGISTER STACK A accumulator PSW processor status word B general purpose C general purpose D general purpose E general purpose H data pointer L data pointer SP Stack Pointer 16-bit address PC Program Counter 16-bit address bit # 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 LOW ORDER BYTE HIGH ORDER BYTE PSW includes the 5 flags: Sign, Zero, None, Aux-Carry, None, Parity, None, Carry 7 6 5 4 3 2 1 0